MPC8280 datasheet(342/1386 Pages) FREESCALE

342 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-34

Freescale Semiconductor

Figure 9-21. General Purpose Control Register (GPCR)

Table 9-8 describes GPCR fields.

Field

—

DMABC

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1087E

Field

—

INTPCI

MCP2PCI

—

LE_MODE

Reset

0000_0000_0000_0000

R/W

Addr

0x1087C

Table 9-8. GPCR Field Descriptions

Bits

Name

Description

31–20

—

Reserved, should be cleared.

19–18

DMABC

DMA 60x bandwidth control

00 DMA uses low 60x bandwidth.

01 DMA uses high 60x bandwidth.

10 DMA uses maximum 60x bus bandwidth.

11 DMA uses minimum 60x bandwidth.

Allows breaks to be inserted in the DMA controller operation. This control may

be needed to avoid starvation of other 60x masters because the PCI bridge can

have higher priorities than other masters. The breaks are inserted only if some

other 60x bus master requests the bus.

The user should find the optimum setting by testing, arriving at the best for each

specific implementation. For most systems the default value (low 60x bandwidth

for the dma) will be good. Note that if the dma is the only master that needs the

bus during the period of the

transfer, the bandwidth is not affected.

17–15

—

Reserved, should be cleared.

INT2PCI

Interrupt reroute to PCI.

0 Interrupts are not rerouted to the PCI. Sent to the core if it is enabled or output

on IRQ7 if the core is disabled.

1 All SIU pending interrupts are rerouted to PCI's INTA. Useful in agent mode.

MCP2PCI

Machine check reroute to PCI.

0 Machine check interrupts are not rerouted to the PCI. Sent to the core if it is

enabled or output on IRQ0 if the core is disabled

1 All machine check interrupts are rerouted to PICE’s INTA. Useful in agent

mode.

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