MPC8280 datasheet(345/1386 Pages) FREESCALE

345 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-37

9.11.1.10 Error Mask Register (EMR)

The error mask register (EMR) register, shown in Figure 9-24, enables the IOU to assert an interrupt or a

machine check for the various types of error conditions listed in Table 9-10. Each mask bit is active high.

That is, if a bit value is zero, an interrupt or machine check is not asserted for the corresponding error

condition.

Figure 9-24. Error Mask Register (EMR)

Table 9-11 describes EMR fields.

PCI_NO_RSP

PCI no response (no DEVSEL; master abort).

PCI_DATA_PAR_RD

PCI read data parity error.

PCI_DATA_PAR_WR

PCI write data parity error.

PCI_ADDR_PAR

PCI address parity error (read or write).

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1088A

Field

—

I2O_

DBMC

NMI

IRA

I2O_

IPQO

I2O_

OFQO

PERR

_WR

PERR

_RD

PCI_

SERR

TAR_

ABT

NO_

RSP

DATA_

PAR_

DATA_

PAR_

ADDR

_PAR

Reset

0000_1111_1111_1111

R/W

Addr

0x10888

Table 9-11. EMR Field Descriptions

Bits

Name

Description

31–13

—

Reserved, should be cleared.

I2O_DBMC

I2O doorbell machine check.

0 Machine check is not enabled

1 Machine check is enabled

NMI

General error/interrupt indication.

IRA

Illegal register access with incorrect size.

I2O_IPQO

I2O inbound post queue overflow.

I2O_OFQO

I2O outbound free queue overflow.

Table 9-10. ESR Field Descriptions (continued)

Bits

Name

Description

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