MPC8280 datasheet(363/1386 Pages) FREESCALE

363 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-55

Figure 9-46. General Purpose Local Access Base Address Registers (GPLABAR

Table 9-33 describes GPLABARx fields.

9.11.2.15 Subsystem Vendor ID Register

Figure 9-47 and Table 9-34 describe the subsystem vendor ID register.

Figure 9-47. Subsystem Vendor ID Register

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x16 (GPLABAR0); 0x1A (GPLABAR1)

Field

PRE

MSI

Reset

0000_0000_0000_0000

R/W

Addr

0x14 (GPLABAR0); 0x18 (GPLABAR1)

Table 9-33. GPLABAR

x Field Descriptions

Bits

Name

Description

31–12

Base address

Represents the base address for the inbound GPLA memory window. The number

of upper bits that the PCI bridge allows to be writable is selected through the PICMR;

see Section 9.11.1.17, “PCI Inbound Comparison Mask Registers (PICMRx).”

11–4

Hardwired to zeros. (The minimum window size allowed is 4K.)

Prefetchable

Corresponds to the prefetchable bit in the PICMR; see Section 9.11.1.17, “PCI

Inbound Comparison Mask Registers (PICMRx).”

2–1

Type

Hardwired to 00 to indicate that the address can be located anywhere in 32-bit

address space.

Memory space indicator Address is mapped to memory space (hardwired to 0).

Field

SVID

Reset

0000_0000_0000_0000

R/W

Addr

0x2C

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