MPC8280 datasheet(367/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-59

9.11.2.22 PCI Bus Function Register

The PCI bus function register, shown in Figure 9-54, is used to determine the configuration of the PCI bus

interface.

Figure 9-54. PCI Bus Function Register

Table 9-41 describes PCI bus function register fields.

Field

—

CFG_LOCK

—

TRGT_

LATENCY_DIS

MSTR_

LATENCY_DIS

PCI_HA

Reset

0000_0000_0010_0000

R/W

Addr

0x44

Table 9-41. PCI Bus Function Register Field Descriptions

Bits

Name

Description

15–6

—

Reserved, should be cleared.

CFG_LOCK

Agent mode: Setting CFG_LOCK prevents an external PCI master from

accessing the configuration space while the 60x bus is doing internal

configuration. It is explicitly set and cleared by the 60x bus.

0 PCI bridge accepts accesses to the PCI configuration space or the internal

memory-mapped configuration space.

1 PCI bridge retries all accesses to the PCI configuration space or the internal

memory-mapped configuration space.

Host mode: the PCI configuration space is not accessible from the PCI side

when the device is in host mode; therefore, this bit applies only for the internal

memory-mapped configuration space.

0 PCI bridge accepts accesses to the internal memory-mapped configuration

space.

1 PCI bridge retries all accesses to the internal memory-mapped configuration

space.

4-3

—

Reserved, should be cleared.

TRGT_LATENCY_DIS

Target latency time-out disable. Controls whether the PCI bridge as a target

time-outs when the first data phase of a transaction has not completed in 16 PCI

cycles.

0 Target latency time-out enabled.

1 Target latency time-out disabled.

MSTR_LATENCY_DIS

Master latency timer disable. Controls whether the PCI bridge as a master ends

a transaction after the expiration of the master latency timer. See

Section 9.11.2.10, “PCI Bus Latency Timer Register.”

0 Master latency timer enabled.

1 Master latency timer disabled.

PCI_HA

Set or cleared by a Power-On configuration bit on power-up and is read-only.

0 PCI interface is in host mode

1 PCI interface is in agent mode

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