MPC8280 datasheet(370/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-62

Freescale Semiconductor

9.11.2.26 PCI Configuration Register Access from the Core

The 60x bus master cannot directly access the PCI configuration registers because they are not in the

internal memory-mapped configuration register’s space. The 60x bus master must first load CFG_ADDR

(at offset 0x10900 in the memory-mapped configuration registers block) with a 32-bit register address in

the form ‘0x8000_0nnn,’ where nnn is the address offset of the desired PCI configuration register. The data

can then be accessed in CFG_DATA (at offset 0x10904 in the internal memory map). See

Section 9.9.1.4.4, “Host Mode Configuration Access.”

When accessing the PCI bridge’s PCI configuration registers with the 60x bus master, note the following:

•

The bus number and device number fields of the CFG_ADDR register should be cleared.

•

Accesses to CFG_ADDR or CFG_DATA which are greater than 4 bytes generate an illegal register

access error setting ECR[IRA]; see Section 9.11.1.11, “Error Control Register (ECR).”

•

Accesses to CFG_DATA without a valid offset in CFG_ADDR generates an I/O transaction on the

PCI bus.

9.11.2.27 PCI Configuration Register Access in Big-Endian Mode

Since the local CPU (internal core or external) is operating in big-endian mode, software must byte-swap

the data of the configuration register before performing an access. That is, the data appears in the core

address and the configuration register data into the core register in ascending significance byte order (LSB

to MSB).

Note that in the following examples, the data in the configuration register (at 0x18) is shown in

little-endian order. This is because all the internal registers are intrinsically little-endian.

Table 9-44. Hot Swap Control Status Register Field Descriptions

Bit

Name

Description

INS

ENUM status: insertion. Write a ‘1’ to clear this bit.

0 ENUM is not asserted

1 ENUM is asserted

EXT

ENUM status: extraction. Write a ‘1’ to clear this bit.

0 ENUM is not asserted

1 ENUM is asserted

21–20

—

Reserved. Should be cleared.

LOO

LED on/off when the hardware is in state H2. Read/write-able.

0 LED off

1 LED on

—

Reserved. Should be cleared.

EIM

ENUM signal mask. Read/write-able.

0 Enable signal

1 Mask signal

—

Reserved. Should be cleared.

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