MPC8280 datasheet(372/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-64

Freescale Semiconductor

executing, care should be taken as to how subsequent accesses to the PCI memory-mapped registers are

made. Consider the following two examples (assume internal memory starts at 0x04700000):

Example 1— Accessing PCI memory-mapped registers before GPCR[LE_MODE] is set. Assume that

one wants to use CPU software to set CTM of PCI DMA0 mode register

(DMAMR0[CTM]) located at 0x04710500. The value constructed from the bit field

description of the DMAMR0 is 0x00000004. However, the value written to this register is

0x04000000—the byte-swapped version of 0x00000004.

Example 2— Accessing PCI memory-mapped registers after GPCR[LE_MODE] is set. Assume that,

after GPCR[LE_MODE] is set, one wants to use CPU software to set DMAMR0[CTM].

Because of address munging, this register is now located at 0x04710504. This new address

is derived from the following:

1.The register is located at 0x04710500.

2.For a 4-byte access, address munging dictates that the XOR value is 0b100 (refer to

Chapter 4 of the Programming Environments Manual for 32-Bit Implementations of

the PowerPC Architecture).

3.The last three bits of 0x04710500 is 0b000.

4.XOR 0b000 with 0b100 (0b000

⊕ 0b100 = 0b100).

5.Therefore, the munged address of this register would be 0x04710504.

Therefore, to set CTM in PCI DMA0 mode register, 0x00000004 is written to 0x04710504.

9.11.2.28 Initializing the PCI Configuration Registers

The configuration registers are initialized to the reset values shown in the register descriptions. However,

they can also be initialized to user-defined values loaded directly from the EEPROM used to configure the

MPC8280 by setting the ALD_EN (auto-load enable) bit in the hard reset configuration word; refer to

Section 5.4.1, “Hard Reset Configuration Word.”

To initialize configuration registers from an EEPROM, the user builds a contiguous table of register

initialization data structures in a user-defined space within the EEPROM. Each data structure, shown in

Figure 9-58, contains the address of a specific register and its initialization data, as well as some control

information. The last data structure entry in the table is marked by setting its ‘Last’ bit.

Figure 9-58. Data Structure for Register Initialization

Offset from the table

start address

0x00

Destination address

0x04

—

Last

Size[1:0]

0x08

Destination data

0x0C

•

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