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MPC8280 Datasheet(PDF) 375 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 375 Page - Freescale Semiconductor, Inc

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PCI Bridge
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
9-67
The interrupt to the local processor is cleared by setting the appropriate bit in the inbound message
interrupt status register. The interrupt to PCI (INTA) is cleared by setting the appropriate bit in the
outbound interrupt status register.
9.12.1.1
Inbound Message Registers (IMR
x)
The inbound message registers, described in Figure 9-60 and Figure 9-46, are accessible from the PCI bus
and the 60x bus in both host and agent modes.
Figure 9-60. Inbound Message Registers (IMR
x)
9.12.1.2
Outbound Message Registers (OMR
x)
The outbound message registers, described in Figure 9-61 and Figure 9-47, are accessible from the PCI
bus and the 60x bus in both host and agent modes.
31
16
Field
IMSG
x
Reset
Undefined
R/W
R/W
Addr
0x10452 (IMR0); 0x10456 (IMR1)
15
0
Field
IMSG
x
Reset
Undefined
R/W
R/W
Addr
0x10450 (IMR0); 0x10454 (IMR1)
Table 9-46. IMR
x Field Descriptions
Bits
Name
Description
31–0
IMSG
x
Inbound message
x. Contains generic data to be passed between the local
processor and external hosts.



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