MPC8280 datasheet(373/1386 Pages) FREESCALE

373 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-65

Table 9-45 describes the data structure fields.

Note that the data structure description assumes the following:

•

Addresses refer to 60x bus addresses.

•

Address and data byte ordering are big-endian.

•

Accesses to PCI configuration registers are indirect (through PCI CFG_ADDR and PCI

CFG_DATA).

A pointer located at address 0x4 of the EEPROM (right after the hard reset configuration word) defines

the beginning of the initialization table. The table should be placed beyond the reset configuration data to

avoid the EEPROM bytes dedicated to the eight possible hard reset configuration words (refer to

Section 5.4.1, “Hard Reset Configuration Word,” and Figure 9-59).

Table 9-45. Bit Settings for Register Initialization Data Structure

Offset

Bits

Name

Description

0x00

0–31

Address

Contains the absolute destination address to which the data is written.

0x04

0–28

—

Reserved, should be cleared.

Last

Indicates that this is the last initialization transaction to be performed.

Not last transaction

Last transaction

30–31

SIZE

Data size in bytes

00 4 bytes

01 1 byte

10 2 bytes

11 3 bytes

0x08

0–31

Data

Contains the data to be written to the specified address. Data bytes are

written according to the value specified in the SIZE field and according

to big-endian byte ordering.

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