MPC8280 datasheet(371/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-63

Example: configuration sequence, 2-byte data write to register at address offset 0x1A for PCI bus.

Initial values:

r0 contains 0x1800_0080

r1 contains IMMR+0x10900

r2 contains IMMR+0x10904

r3 contains 0xDDCC_BBAA

Code sequence:

stw

r0,0(r1)

sth

r3,2(r2)

Results: Address IMMR+0x10900 contains 0x8000_0018 (MSB to LSB)

Address IMMR+0x10904 contains 0xXXXX_AABB (MSB to LSB) where ‘XXXX’ is

the old value and is not affected the sth.

Note: the address of PCI_CFG_DATA must match the offset address 0x1A.

This example shows an address of IMMR+0x10906 used to access the PCI_CFG_DATA. This was done

in order to align the data with the address 0x1A. The address used to access PCI_CFG_DATA can have a

value of IMMR+0x10904, IMMR+0x10905, IMMR+0x10906, or IMMR+0x10907. The two least

significant bits of the address used to access PCI_CFG_DATA should match the byte-wise offset of the

used to access PCI_CFG_DATA must be IMMR+0x10905.

9.11.2.27.1

Additional Information on Endianess

The endianess of both the MPC8280's peripheral logic (GPCR[LE_MODE]—see the following section)

and the MPC8280's 603e CPU core (MSR[LE]) must be set to the same endianess configuration—that is

both must be set for little or big endian operation.

For applications where little endian (LE) devices, such as those commonly found on the PCI bus, share

memory with the MPC8280, it is recommended to leave the MPC8280's 603e core CPU and peripheral

logic in the big endian (BE) modes and then to use a region of the MPC8280 local memory for

LE-formatted data. When a little endian PCI device stores data to this memory region, the MPC8280

internal peripheral logic (in big endian mode) stores the data into memory in LE format. Likewise, when

a little-endian PCI device reads data from this memory region, the MPC8280 internal peripheral logic (in

BE mode) provides the data to the PCI device in LE format.

A little-endian PCI device can share this LE memory region with the MPC8280 local processor (603e core

CPU) running in big endian if, when the MPC8280 accesses that LE region, it uses the lwbrx and stwbrx

commands. The lwbrx command byte-swaps the LE data from that region so the 603e CPU sees the data

in BE format. Similarly, the stwbrx command byte-swaps the BE data from the 603e processor being

stored to that region of memory, so it is stored into the memory region in LE format.

For the MPC603e and the MPC8280 implementations, there is NO latency difference associated with

lwbrx and stwbrx commands compared to the other load and store commands.

9.11.2.27.2

Notes on GPCR[LE_MODE]

GPCR[LE_MODE] (refer to Section 9.11.1.7) determines the endianess of the PCI section of MPC8280.

The default value of GPCR[LE_MODE] (offset: 0x1087C) is 0. If LE_MODE is set while a program is

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