MPC8280 datasheet(368/1386 Pages) FREESCALE

368 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-60

Freescale Semiconductor

9.11.2.23 PCI Bus Arbiter Configuration Register

The PCI bus arbiter configuration register, shown in Figure 9-55, is used to determine the configuration of

the PCI bus arbiter. Only 1-byte or 2-byte accesses to address offset 0x46 are allowed.

Figure 9-55. PCI Bus Arbiter Configuration Register

Table 9-42 describes the PCI bus arbiter configuration register fields.

Field

PCI_

ARB_DIS

—

PCI_BUSMP

—

PCI_

BRIDGE MP

Reset

01000_0000_0000_0000

1 Reset value determined by PIC_CFG[1] pin value after hard reset. Refer to Table 9-42.

R/W

Addr

0x46

Table 9-42. PCI Bus Arbiter Configuration Register Field Description

Bit

Name

Description

PCI_ARB_DIS

(PCI_CFG[1] pin value)

Determines if the PCI bridge is the PCI arbiter on the PCI bus. Set or cleared by

the PIC_CFG[1] pin value after hard reset.

0 PCI bridge is the PCI arbiter.

1 PCI bridge is not the PCI arbiter. The PCI bridge presents its request on REQ0

to the external arbiter and receives its grant on GNT0.

Parking Mode

Controls which device receives the bus grant when there are no outstanding bus

requests and the bus is idle.

0 The bus is parked with the last device to use the bus.

1 The bus is parked with the PCI bridge.

13–7

—

Reserved, should be cleared.

6-4

PCI Bus Master

Priorities

Determines the arbitration priority given to the different masters on the PCI bus.

Bit 6 corresponds to the priority of the master sourcing REQ0, bit 5 corresponds

to REQ1, and bit 4 corresponds to REQ2.

Master

n has a low priority.

Master

n has a high priority.

3–1

—

Reserved, should be cleared.

PCI Bridge Master

Priority

Determines the PCI bridge’s arbitration priority.

0 The PCI bridge has a low priority.

1 The PCI bridge has a high priority.

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