MPC8280 datasheet(377/1386 Pages) FREESCALE

377 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-69

Figure 9-62. Outbound Doorbell Register (ODR)

9.12.2.2

Inbound Doorbell Register (IDR)

IDR, described in Figure 9-63 and Table 9-49, is accessible from the PCI bus and the 60x bus in both host

and agent modes.

Figure 9-63. Inbound Doorbell Register (IDR)

Field

—

ODR

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-48.

Addr

0x10462

Field

ODR

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-48.

Addr

0x10460

Table 9-48. ODR Field Descriptions

Bits

Name

Access

Description

31–29

—

Reserved, should be cleared.

28–0

ODR

Write 1 to set from local processor.

Write 1 to clear from PCI.

Outbound door bell

x, where x is each bit. Writing a bit in

this register from the local processor causes an interrupt

(INTA) to be generated.

Field IMC

IDR

Reset

0000_0000_0000_0000

R/W

Addr

0x1046A

Field

IDR

Reset

0000_0000_0000_0000

R/W

Addr

0x10468

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