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MPC8280 Datasheet(PDF) 382 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 382 Page - Freescale Semiconductor, Inc |
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382 / 1386 page ![]() PCI Bridge MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 9-74 Freescale Semiconductor Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHPR) MFAs posted by PCI hosts are picked up by the local processor via the inbound post_FIFO tail pointer register, described in Figure 9-68 and Table 9-53. The local processor is responsible for updating this register. Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR) 31 20 19 16 Field QBA IPHP Reset 0000_0000_0000_0000 R/W R R/W Addr 0x104B2 15 21 0 Field IPHP — Reset 0000_0000_0000_0000 R/W R/W R Addr 0x104B0 Table 9-52. IPHPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20. 19–2 IPHP Inbound post_FIFO head pointer. Local memory offset of the head pointer of the inbound post list FIFO. 1–0 — Reserved, should be cleared. 31 20 19 16 Field QBA IPTP Reset 0000_0000_0000_0000 R/W R R/W Addr 0x104BA 15 21 0 Field IPTP — Reset 0000_0000_0000_0000 R/W R/W R Addr 0x104B8 |
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