MPC8280 datasheet(384/1386 Pages) FREESCALE

384 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-76

Freescale Semiconductor

Free MFAs are picked up by the local processor pointed to by the outbound free_FIFO tail pointer register,

described in Figure 9-70 and Table 9-55. This register is updated by the local processor.

Figure 9-70. Outbound Free_FIFO Tail Pointer Register (OFTPR)

9.12.3.3.2

Outbound Post_FIFO Head Pointer Register (OPHPR) and

Outbound Post_FIFO Tail Pointer Register (OPTPR)

The outbound post FIFO holds MFAs which are posted from the local processor to external processors.

The local processor places messages in the outbound post FIFO by writing to the MFA to OPHPR +

QBAR. The local processor must then advance the OPHPR.

The PCI bridge’s PCI interrupt is generated (INTA) when the FIFO is not empty (head and tail pointers are

not equal). The outbound post queue interrupt bit is set in the outbound interrupt status register. The status

bit is cleared when the head and tail pointers are equal. The interrupt can be masked using the outbound

interrupt mask register.

Table 9-54. OFHPR Field Descriptions

Bits

Name

Description

31–20

QBA

Queue base address. When read returns the contents of QBAR.

19–2

OFHP

Outbound free_FIFO head pointer. Local memory offset of the head pointer of the outbound free

list FIFO.

1–0

—

Reserved, should be cleared.

Field

QBA

OFTP

Reset

0000_0000_0000_0000

R/W

Addr

0x104CA

Field

OFTP

—

Reset

0000_0000_0000_0000

R/W

Addr

0x104C8

Table 9-55. OFTPR Field Descriptions

Bits

Name

Description

31–20

QBA

Queue base address. When read returns the contents of QBAR bits 31-20.

19–2

OFTP

Outbound free_FIFO tail pointer. Local memory offset of the tail pointer of the outbound free list

FIFO.

1–0

—

Reserved, should be cleared.

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