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MPC8280 Datasheet(PDF) 383 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 383 Page - Freescale Semiconductor, Inc

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PCI Bridge
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
9-75
9.12.3.3
Outbound FIFOs
The outbound queues are used to send messages from the local processor to a remote host processor. I2O
defines two outbound FIFOs—an outbound post FIFO and an outbound free FIFO.
The following registers should be accessed only from the 60x bus and only in agent mode. Accesses while
in host mode or from the PCI bus have undefined results.
9.12.3.3.1
Outbound Free_FIFO Head Pointer Register (OFHPR) and
Outbound Free_FIFO Tail Pointer Register (OFTPR)
The outbound free list FIFO holds the MFAs of the empty outbound message locations in local memory.
When the local processor is ready to send an outbound message, it first fetches an empty MFA by reading
the OFTPR. It then writes the message into the MFA. The OFTPR is managed by the local processor.
When an external PCI master has completed use of a message that was posted in the outbound post FIFO
and wants to return the MFA to the free list, it writes to OFQPR (refer to Section 9.12.3.4.2, “Outbound
FIFO Queue Port Register (OFQPR)”). The PCI bridge’s I2O unit then writes the MFA to the OFHPR.
This, in turn, causes the outbound free head pointer to be advanced.
Free MFAs are returned by the PCI masters to the outbound free list FIFO that is pointed to by the
outbound free_FIFO head pointer register, described in Figure 9-69 and Table 9-54. The PCI write
references the outbound queue port. The I2O hardware automatically advances the address, (i.e. OFHPR)
after every write.
Figure 9-69. Outbound Free_FIFO Head Pointer Register (OFHPR)
Table 9-53. IPTPR Field Descriptions
Bits
Name
Description
31–20
QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
IPTP
Inbound post_FIFO tail pointer. Local memory offset of the tail pointer of the inbound post list
FIFO.
1–0
—
Reserved, should be cleared.
31
20
19
16
Field
QBA
OFHP
Reset
0000_0000_0000_0000
R/W
R
R/W
Addr
0x104C2
15
21
0
Field
OFHP
—
Reset
0000_0000_0000_0000
R/W
R/W
R
Addr
0x104C0



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