MPC8280 datasheet(422/1386 Pages) FREESCALE

422 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-2

Freescale Semiconductor

•

18-bit address and 32-bit local data bus memory controller. The local bus memory controller

supports the following:

— 8-, 16-, and 32-bit port sizes

— Parity checking and generation

— Ability to work in parallel with the 60x bus memory controller

•

Flexible chip-select assignment—The 60x bus and local bus share twelve chip-select lines

(controlled by a memory controller bank). The user can allocate the twelve banks as needed

between the 60x bus and the local bus.

•

Flexible UPM assignment—The user can assign any of the three UPMs to the 60x bus or the Local

bus

Figure 11-1 shows the dual-bus architecture.

Figure 11-1. Dual-Bus Architecture

MPC8280

A[0–31]

D[0–63]

LA[14–31]

LD[0–31]

External

Master

60x

Local

60x Memory

Control Signals

CS[0–11]

Local Memory

Control Signals

60x Address

Bus Interface

Local Address

Bus Interface

Local Data

Bus Interface

60x Address [0–31]

Local Address [0–31]

60x Data[0–63]

Local Data [0–63]

GPCM

SDRAM

Local

Memory

Controller

SDRAM

GPCM

60x

Memory

Controller

3 UPM

Arrays

Local

60x-to-Local

Core

CPM/Local

60x

Transactions

60x Data

Bus Interface

CPM/PCI

Master

Slave

Memory

Devices

Memory

Devices

MPC8280 Datasheet(PDF) 422 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 422 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL