MPC8280 datasheet(423/1386 Pages) FREESCALE

423 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-3

11.1

Features

The memory controller’s main features are as follows:

•

Twelve memory banks

— 32-bit address decoding with mask

— Variable block sizes (32 Kbytes to 4 Gbytes)

— Three types of data errors check/correction:

– Normal odd/even parity

– Read-modify-write (RMW) odd/even parity for single accesses

–ECC

— Write-protection capability

— Control signal generation machine selection on a per-bank basis

— Flexible chip-select assignment between the 60x bus and the local bus

— Supports internal or external masters on the 60x bus

— Data buffer controls activated on a per-bank basis

— Atomic operation

— Extensive external memory-controller/bus-slave support

— ECC/parity byte-select

— Data pipeline to reduce data setup time for synchronous devices

•

Synchronous DRAM machine (60x or local bus)

— Provides the control functions and signals for glueless connection to JEDEC-compliant

SDRAM devices

— Back-to-back page mode for consecutive, back-to-back accesses

— Supports 2-, 4- and 8-way bank interleaving

— Supports SDRAM port size of 64-bit (60x only), 32-bit, 16-bit and 8-bit

— Supports external address and/or command lines buffering

•

General-purpose chip-select machine (GPCM)—60x or local bus

— Compatible with SRAM, EPROM, FEPROM, and peripherals

— Global (boot) chip-select available at system reset

— Boot chip-select support for 8-, 16-, 32-, and 64-bit devices

— Minimum two clock accesses to external device

— Eight byte write enable signals (WE)—four on the local bus

— Output enable signal (OE)

— External access termination signal (GTA)

•

Three UPMs

— Each machine can be assigned to the 60x or local bus.

— Programmable-array-based machine controls external signal timing with a granularity of up to

one quarter of an external bus clock period

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