MPC8280 datasheet(431/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-11

11.2.13 Partial Data Valid Indication (PSDVAL)

The 60x and local buses have an internal 64-bit data bus. According to the 60x bus specification, TA is

asserted when up to a double word of data is transferred. Because the MPC8280 supports memories with

port sizes smaller than 64 bits, there is a need for partial data valid indication. The memory controller uses

PSDVAL to indicate that data is latched by the memory on write accesses or valid data is present on read

accesses. The quantity of the data depends on the memory port size and the transfer size. The memory

controller accumulates PSDVAL assertions, and when a double word (or the transfer size) is transferred,

the memory controller asserts TA to indicate that a 60x data beat was transferred. Table 11-1 shows the

number of PSDVAL assertions needed for one TA assertion under various circumstances.

Figure 11-5 shows a double-word transfer on 32-bit port size memory.

Figure 11-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer

Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion

Port Size

Transfer Size

PSDVAL Assertions

TA Assertions

Any

Double word

Word/half word/byte (32-bit aligned)

Double Word

Word

Half/byte

Double word

Word

8Half

8Byte

Clock

External

PSDVAL

Internal

Data Bus

(32 msb)

Upper 4 bytes

Lower 4 bytes

Internal

Data Bus

(32 lsb)

Upper 4 bytes

Lower 4 bytes

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