MPC8280 datasheet(428/1386 Pages) FREESCALE

428 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-8

Freescale Semiconductor

11.2.2

Page Hit Checking

The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM

device, the SDRAM machine stores its address in a page register. The page information, which the user

writes to the ORx register, is used along with the bank size to compare page bits of the address to the page

cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus

becomes idle, unless ORx[PMS] is set.

11.2.3

Error Checking and Correction (ECC)

ECC can be configured for any bank as long as it is assigned to the 60x bus and is connected to a 64-bit

port size memory. ECC is generated and checked on a 64-bit basis using DP[0–7] for the bank if

BRx[DECC] = 11. If ECC is used, single errors can be corrected and all double-bit errors can be detected.

11.2.4

Parity Generation and Checking

Parity can be configured for any bank, if it is preferred. Parity is generated and checked on a per-byte basis

using DP[0–7] or LDP[0–3] for the bank if BR[DECC] = 01 for normal parity and 10 for RMW parity.

SIUMCR[EPAR] determines the global type of parity (odd or even).

Note that RMW parity can be used only for 32- or 64-bit port size banks. Also, using RMW parity on a

32-bit port size bank requires that the bus is placed in strict 60x mode. This is done by setting BCR[ETM]

(BCR[LETM] for the local bus). Refer to Section 4.3.2.1, “Bus Configuration Register (BCR).”

NOTE: RMW Parity and ECC Modes and Pipelined Addresses

Due to design constraints, using RMW parity or ECC modes and pipelined

addresses (BCR[PLDP] = 0) on the SDRAM interface, requires that the

PSDMR[CL] will be set to 10, choosing CAS latency of 2. If CAS latency

of 3 is needed, use BCR[PLDP] = 1 for a pipeline depth of zero.

When the MPC8280 is decoding a 60x read transaction into one of its internal memory-mapped registers

or dual-port RAM that was originated by an external 60x master, it will generate parity bits along with the

data bytes on DP[0–7]. The type of parity (odd or even) is determined by the SIUMCR[EPAR]

programming.

11.2.5

Transfer Error Acknowledge (TEA) Generation

The memory controller asserts the transfer error acknowledge signal (TEA) in the following cases:

•

An unaligned or burst access is attempted to internal MPC8280 space (registers or dual-port

RAM). Note that the dual-port RAM cannot be accessed via bursts.

•

The core or an external master attempts a burst access to the local bus address space

•

A bus monitor timeout

MPC8280 Datasheet(PDF) 428 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 428 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL