MPC8280 datasheet(438/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-18

Freescale Semiconductor

BCTLD Data buffer control disable. Disables the assertion of BCTL

x (60x bus) and LWR (local bus) during

an access to the current memory bank. See Section 11.2.7, “Data Buffer Controls (BCTLx and

LWR).”

0BCTL

x and LWR are asserted upon an access to the current memory bank.

1BCTL

x and LWR are not asserted upon an access to the current memory bank.

CSNT

Chip-select negation time. Determines when CS/WE are negated during an external memory write

access handled by the GPCM. This helps meet address/data hold times for slow memories and

peripherals.

0CS/WE are negated normally.

1CS/WE are negated a quarter of a clock earlier. (default)

Note: After system reset OR0[CSNT] is set.

21–22

ACS

Address to chip select setup. Can be used when the external memory access is handled by the

GPCM. It allows the delay of the CS assertion relative to the address change.

00 CS is output at the same time as the address lines

01 Reserved

10 CS is output a quarter of a clock after the address lines

11 CS is output half a clock after the address lines (default)

Note: After a system reset, OR0[ACS] = 11.

—

Reserved, should be cleared.

24–27

SCY

Cycle length in clocks. Determines the number of wait states inserted in the cycle, when the GPCM.

handles the external memory access. Thus it is the main parameter for determining cycle length.

The total cycle length depends on other timing attribute settings.

The total memory access length is (2 + SCY) x Clocks.

If the user selects an external PSDVAL response for this memory bank (by setting the SETA bit),

write a non-zero values to SCY.

0000 = 0 clock cycle wait states...1111 = 15 clock cycles wait states

Note: After a system reset, OR0[SCY] = 1111.

Note: Refer to the note immediately following this table.

SETA

External access termination (PSDVAL generation). Used to specify that when the GPCM is selected

to handle the memory access initiated to this memory region, the access is terminated externally by

asserting the GTA external pin. In this case, PSDVAL is asserted one or two clocks later, depending

on the synchronization of GTA. See Section 11.5.2, “External Access Termination.”

0 PSDVAL is generated internally by the memory controller unless GTA is asserted earlier

externally.

1 PSDVAL is generated after external logic asserts GTA.

Note: After a system reset, the OR0[SETA] is cleared.

TRLX

Timing relaxed. Works in conjunction with EHTR.

EHTR

Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between

a read access from the current bank and the next write access to the same bank, or any type of

access to another bank. It does not affect subsequent read accesses to the same bank.

TRLX and EHTR work together and are interpreted as follows:

00 Normal timing is generated by the memory controller. No additional cycles are inserted.

01 One idle clock cycle is inserted.

10 Four idle clock cycles are inserted. (default)

11 Eight idle clock cycles are inserted.

—

Reserved, should be cleared.

Table 11-6. OR

x—GPCM Mode Field Descriptions (continued)

Bits

Name

Description

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