MPC8280 datasheet(440/1386 Pages) FREESCALE

440 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-20

Freescale Semiconductor

11.3.3

60x SDRAM Mode Register (PSDMR)

The 60x SDRAM mode register (PSDMR), shown in Figure 11-10, is used to configure operations

pertaining to SDRAM.

Table 11-8 describes PSDMR fields. LSMDR fields are described in Table 11-9.

Burst inhibit. Indicates if this memory bank supports burst accesses.

0 The bank supports burst accesses

1 The bank does not support burst accesses. The UPMx executes burst accesses as series of

single accesses.

24–28

—

Reserved, should be cleared.

29–30

EHTR

Extended hold time on read accesses. Indicates how many cycles are inserted between a read

access from the current bank and the next access.

00 Normal timing is generated by the memory controller. No additional cycles are inserted.

01 One idle clock cycle is inserted.

10 Four idle clock cycles are inserted.

11 Eight idle clock cycles are inserted.

—

Reserved, should be cleared.

Field

PBI

RFEN

SDAM

BSMA

SDA10

RFRC

Reset

0000_0000_0000_0000

R/W

Addr

0x10190 (PSDMR), 0x10194 (LSDMR)

Field RFRC

PRETOACT

ACTTORW

LDOTOPRE

WRC

EAMUX BUFCMD

Reset

0000_0000_0000_0000

R/W

Addr

0x10192 (PSDMR), 0x10196 (LSDMR)

Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)

Table 11-7. Option Register (OR

x)—UPM Mode (continued)

Bits

Name

Description

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