MPC8280 datasheet(441/1386 Pages) FREESCALE

441 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-21

Table 11-8. PSDMR Field Descriptions

Bits

Name

Description

PBI

Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction

with PSDMR[SDA10]. See Section 11.4.5, “Bank Interleaving.”

0 Bank-based interleaving (default at reset)

1 Page-based interleaving (recommended operation)

RFEN

Refresh enable. Indicates that the SDRAM needs refresh services.

0 Refresh services are not required

1 Refresh services are required

Note: After system reset, RFEN is cleared.

See Section 11.3.8, “60x Bus-Assigned UPM Refresh Timer (PURT),” Section 11.3.9, “Local

Bus-Assigned UPM Refresh Timer (LURT),” Section 11.3.10, “60x Bus-Assigned SDRAM

Refresh Timer (PSRT),” and Section 11.3.11, “Local Bus-Assigned SDRAM Refresh Timer

(LSRT).”

2–4

SDRAM operation. Determines which operation occurs when the SDRAM device is accessed.

000 Normal operation

001 CBR refresh, used in SDRAM initialization.

010 Self refresh (for debug purpose).

011 Mode Register write, used in SDRAM initialization.

Note that if 60x-compatible mode is in effect on the 60x bus or the SDRAM port size is 8/16 or

the SDRAM is connected to the BADDR lines (not needed for 64/32 port size), the bus master

must supply the mode register data on the low bits of the address during the access.

100 Precharge bank (for debug purpose).

101 Precharge all banks, used in SDRAM initialization.

110 Activate bank (for debug purpose).

111 Read/write (for debug purpose).

5–7

SDAM

Address multiplex size. Determines how the address of the current memory cycle can be output

on the address pins. See Section 11.4.5.2, “SDRAM Address Multiplexing (SDAM and BSMA).”

8–10

BSMA

Bank select multiplexed address line. Selects the address pins to serve as bank-select address

for the 60x SDRAM. The bank select address can also be output on the BANKSEL pins

(optional). See Section 11.4.5.2, “SDRAM Address Multiplexing (SDAM and BSMA).”

000 A12–A14

001 A13–A15

010 A14–A16

011 A15–A17

100 A16–A18

101 A17–A19

110 A18–A20

111 A19–A21

11–13

SDA10

“A10” control. With PSDMR[PBI], determines which address line can be output to SDA10 during

an ACTIVATE command, when SDRAM is selected, to control the memory access. See

Section 11.4.12.1, “SDRAM Configuration Example (Page-Based Interleaving).”

For PBI = 0:

000 A12

001 A11

010 A10

011 A9

100 A8

101 A7

110 A6

111 A5

For PBI = 1:

000 A10

001 A9

010 A8

011 A7

100 A6

101 A5

110 A4

111 A3

MPC8280 Datasheet(PDF) 441 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 441 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL