MPC8280 datasheet(450/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-30

Freescale Semiconductor

Table 11-12 describes MAR fields.

11.3.8

60x Bus-Assigned UPM Refresh Timer (PURT)

The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 11-14.

Table 11-13 describes PURT fields.

11.3.9

Local Bus-Assigned UPM Refresh Timer (LURT)

The local bus assigned UPM refresh timer register (LURT) is shown in Figure 11-15.

Table 11-12. MAR Field Description

Bits

Name

Description

0–31

Memory address. The memory address register can be output to the address lines under control of

the AMX bits in the UPM

Field

PURT

Reset

0000_0000

R/W

Addr

0x10198

Figure 11-14. 60x Bus-Assigned UPM Refresh Timer (PURT)

Table 11-13. 60x Bus-Assigned UPM Refresh Timer (PURT)

Bits

Name

Description

0–7

PURT

Refresh timer period. Determines the timer period according to the following equation:

This timer generates a refresh request for all valid banks that selected a UPM machine assigned to

the 60x bus (M

xMR[BSEL] = 0) and is refresh-enabled (MxMR[RFEN] = 1). Each time the timer

expires, a qualified bank generates a refresh request using the selected UPM. The qualified banks

are rotating their requests.

Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given

MPTPR[PTP] = 31, the PURT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less

than the required service period of 15.6 µs.

Field

LURT

Reset

0000_0000

R/W

Addr

0x101A0

Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT)

TimerP eriod

PURT

()

MPTPR PTP

[] 1

()

Bus Frequency

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