MPC8280 datasheet(446/1386 Pages) FREESCALE

446 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-26

Freescale Semiconductor

11.3.5

Machine A/B/C Mode Registers (M

xMR)

The machine x mode registers (MxMR), shown in Figure 11-11, contain the configuration for the three

UPMs.

EAMUX

External address multiplexing enable/disable.

0 No external address multiplexing. Fastest timing.

1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE

command to the SDRAM. This is useful when external address multiplexing can cause a

delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least two.

In local bus mode, external address multiplexing is placed on the address lines. If the additional

delay of the multiplexing endangers the device setup time, EAMUX should be set. Setting this

bit causes the memory controller to add another cycle for each address phase.

Note: EAMUX can also be set in case of address line delays, such as address buffers. See

Section 11.4.6.7, “External Address Multiplexing Signal.”

BUFCMD

If external buffers are placed on the control lines going to both the SDRAM and address lines,

setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,

instead of one. See Section 11.4.6.8, “External Address and Command Buffers (BUFCMD).”

0 Normal timing for the control lines

1 All control lines except CS are asserted for two cycles

In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,

as well as the address lines. If the additional delay of the buffers is endangering the device

setup time, BUFCMD should be set to cause the memory controller to add another cycle for

each SDRAM command.

30–31

CAS latency. Defines the timing for first read data after a column address is sampled by the

SDRAM. See Section 11.4.6.3, “Column Address to First Data Out—CAS Latency.”

00 Reserved

01 1 clock cycle

10 2 clock cycles

11 3 clock cycles

Field BSEL RFEN

—

DSx

G0CLx

GPL_x4DIS

RLFx

Reset

0000_0000_0000_0

R/W

Addr

0x10170 (MAMR); 0x10174 (MBMR); 0x10178 (MCMR)

Field

RLFx

WLF

TLF

MAD

Reset

0000_0000_0000_0000

R/W

Addr

0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR)

Figure 11-11. Machine

x Mode Registers (MxMR)

Table 11-9. LSDMR Field Descriptions (continued)

Bits

Name

Description

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