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MPC8280 Datasheet(PDF) 529 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 529 Page - Freescale Semiconductor, Inc |
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529 / 1386 page  Secondary (L2) Cache Support MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 12-3 and its associated latency. Thus, reads are serviced just as they are for copy-back mode. Write-through mode sacrifices some of the write performance of copy-back mode, but guarantees L2 cache coherency with main memory. Since write-through mode keeps memory coherent with the contents of the L2 cache, there is never any need to perform an L2 copy-back. This removes the need for the L2 cache to maintain a dirty bit in the tag RAM (all cache blocks are unmodified) and it also removes the need for bus arbitration signals. The L2 cache is configured for write-through mode by pulling down it’s WT signal. There are no configuration changes to the MPC8280 required in write-through mode. The MPC8280 can also support additional bus masters (60x or MPC8280-type) in write-through mode. Figure 12-2 shows a MPC8280 connected to a MPC2605 integrated L2 cache in write-through mode. |
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