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MPC8280 Datasheet(PDF) 530 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 530 Page - Freescale Semiconductor, Inc |
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530 / 1386 page  Secondary (L2) Cache Support MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 12-4 Freescale Semiconductor Figure 12-2. External L2 Cache in Write-Through Mode 12.1.3 ECC/Parity Mode ECC/parity mode is a subset of write-through mode with some connection changes that allow the L2 cache to support ECC or Parity. The connection changes are: • The MPC8280’s DP[0:7] signals are connected to the L2 cache’s DP[0:7] signals. • The L2’s TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction size. • The L2’s A[29:31] signals are pulled down. BR DBG TS, TT[0:4], TBST, TSIZ[1–3] A[0–31] CI, GBL, TA, DBB, TEA CPU_BR, CPU_BG, CPU_DBG D[0–63] MPC8280 L2BR L2DBG TS, TT[0–4], TBST, TSIZ[0–2] CI, GBL, TA, DBB, TEA AACK, ARTRY AACK, ARTRY CPU_BR,CPU_BG,CPU_DBG L2_CLAIM L2_HIT A[0–31] D[0–63] Memory Controller SDRAM Main Memory Latch MUX I/O Devices MPC2605 BG L2BG TSIZ[0] (pull down) WT (pull down) (pull up) (pull up) |
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