MPC8280 datasheet(533/1386 Pages) FREESCALE

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Secondary (L2) Cache Support

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

12-7

•

BCR[L2D] = 0—L2 response time. In this case, the L2 will claim a bus transaction one clock cycle

after TS assertion.

•

BCR[APD] = 1: This parameter is not L2 specific, but should consider the L2 ARTRY assertion

timing.

See Section 4.3.2.1, “Bus Configuration Register (BCR),” for more details about these parameters.

12.3

System Requirements When Using the L2 Cache Interface

The following requirements apply to MPC8280-based systems that implement an external L2 cache:

•

For systems that use copy-back mode, all cachable memory regions must be marked as global in

the CPU’s MMU and the CPM. This causes the assertion of the GBL signal on every cachable

transaction. Systems that use write-through mode (or ECC/Parity mode) have no such restriction.

•

All cachable memory regions must have a 64-bit port size.

•

All cachable memory regions must not set the BRx[DR] bit.

•

All cachable memory regions must not use ECC or parity unless the external L2 is connected as

described in Section 12.1.3, “ECC/Parity Mode.”

•

All non-cachable memory regions must be marked as caching-inhibited in the CPU’s MMU. This

causes the assertion of the CI signal on every non-cachable transaction. Note that the MPC8280’s

internal space (IMMR) and any memory banks assigned to the local bus are always considered

non-cachable.

12.4

L2 Cache Operation

When configured for an L2 cache (BCR[L2C] = 1), the MPC8280 samples the L2_HIT input signal when

the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if L2_HIT is asserted, the external

L2 cache drives AACK and TA to complete the transaction without the MPC8280 initiating a system

memory transfer.

The external L2 cache can assert ARTRY to retry 60x bus cycles, and can request the bus by asserting BR

to perform L2 cast-out operations. The arbiter grants the address and data bus to the external L2 cache by

asserting BG and DBG, respectively. If the external L2 cache asserts ARTRY, it should not assert L2_HIT.

For more information about the timing and behavior of the MPC2605 integrated L2 cache, refer to the

MPC2605 data sheet.

12.5

Timing Example

Figure 12-4. shows a read access performed by the MPC8280 with an externally controlled L2 cache. For

the first transaction (A0), the MPC8280 grants the bus and asserts TS with the address and address transfer

attributes. In this example, BCR[L2D] = 0, which means that L2_HIT is valid one clock cycle after the

assertion of TS. The MPC8280 samples L2_HIT when L2D expires. In the second transaction (A1), the

access misses in the L2 cache and the memory controller starts the transaction a minimum of three cycles

after the assertion of TS.

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