MPC8280 datasheet(539/1386 Pages) FREESCALE

539 / 1386 page

IEEE 1149.1 Test Access Port

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

13-5

Figure 13-5. Output Control Cell (IO.CTL)

Figure 13-6. General Arrangement of Bidirectional Pin Cells

The control bit value controls the output function of the bidirectional pin. One or more bidirectional data

cells can be serially connected to a control cell. Bidirectional pins include two scan cell for data (IO.Cell)

as shown in Figure 13-6 and these bits are controlled by the cell shown in Table 13-5.

13.4

Instruction Register

The MPC8280 JTAG implementation includes the public instructions (EXTEST, SAMPLE/PRELOAD,

and BYPASS) and also supports the CLAMP instruction. One additional public instruction (HI-Z) can be

used to disable all device output drivers. The MPC8280 includes an 8-bit instruction register (no parity)

that consists of a shift register with four parallel outputs. Data is transferred from the shift register to the

MUX

From Last Cell

Clock DR

Update DR

Shift DR

1 — EXTEST | Clamp

To Output

Buffer

0 — Otherwise

To Next Cell

Output Control

Logic

from System

I/O

From Last Cell

Output Data

Input Data

Output Enable

I.OBS

from System Logic

O.PIN

I/O.CTL

To Next Pin Pair

To Next Cell

MPC8280 Datasheet(PDF) 539 Page - Freescale Semiconductor, Inc