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MPC8280 Datasheet(PDF) 541 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 541 Page - Freescale Semiconductor, Inc |
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541 / 1386 page ![]() IEEE 1149.1 Test Access Port MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 13-7 The parallel output of the instruction register is set to all ones in the test-logic-reset controller state. Notice that this preset state is equivalent to the BYPASS instruction. During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the CLAMP command code. 13.5 MPC8280 Restrictions The control afforded by the output enable signals using the boundary-scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the MPC8280’s output drivers are enabled into actively driven networks. 13.6 Nonscan Chain Operation In nonscan chain operation, the TCK input does not include an internal pull-up resistor and should be tied high or low to preclude mid-level inputs. To ensure that the scan chain test logic is kept transparent to the system logic, the TAP controller is forced into the test-logic-reset state. This is done inside the chip by connecting TRST to PORESET TMS should remain logic high, so that the TAP controller does not leave the test-logic-reset state. 1 1 1 1 0 0 0 0 HI–Z Provided as a manufacturer’s optional public instruction to avoid back driving the output pins during circuit-board testing. When HI-Z is invoked all output drivers, including the two-state drivers, are turned off (high impedance). The instruction selects the bypass register. 1 1 1 100 01 CLAMP and BYPASS CLAMP selects the single-bit bypass register as shown in the BYPASS instruction figure above, and the state of all signals driven from the system output pins is completely defined by the data previously shifted into the boundary scan register. For example, using the SAMPLE/PRELOAD instruction. 1 B0 (lsb) is shifted first. Table 13-2. Instruction Decoding (continued) Code1 Instruction Description B7 B6 B5 B4 B3 B2 B1 B0 |
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