MPC8280 datasheet(808/1386 Pages) FREESCALE

808 / 1386 page

SCC Ethernet Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

25-20

Freescale Semiconductor

Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”

25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)

The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts and report

events recognized by the Ethernet channel. When an event is recognized, the Ethernet controller sets the

corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in

the Ethernet mask register (SCCM). SCCE bits are cleared by writing ones; writing zeros has no effect.

All unmasked bits must be cleared before the CPM clears the internal interrupt request. The SCCE/SCCM

registers are displayed in Figure 25-9.

Table 25-9 describes SCCE and SCCM fields.

Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully

transmit a message because of repeated collisions on the medium. The Ethernet controller writes

this bit after it finishes attempting to send the buffer.

10–13

Retry count. Indicates the number of retries required before the frame was sent successfully. If RC

= 0, the frame was sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM,

15 retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then

15 or more retries were required. The controller writes this field after it successfully sends the buffer.

Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the

buffer. The Ethernet controller writes UN after it finishes sending the buffer.

CSL

Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller

writes CSL after it finishes sending the buffer.

Field

—

GRA

—

TXE

RXF

BSY

TXB

RXB

Reset

0000_0000_0000_0000

R/W

Addr

0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)

0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)

Figure 25-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)

Table 25-9. SCCE/SCCM Field Descriptions

Bits

Name

Description

0–7

—

Reserved, should be cleared.

GRA

Graceful stop complete. Set as soon the transmitter finishes any frame that was in progress when

a GRACEFUL STOP TRANSMIT command was issued. It is set immediately if no frame was in progress.

9–10

—

Reserved, should be cleared.

TXE

Set when an error occurs on the transmitter channel. This event is not maskable via the TxBD[I] bit.

RXF

Rx frame. Set when a complete frame has been received on the Ethernet channel.

Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions (continued)

Bits

Name

Description

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