MPC8280 datasheet(827/1386 Pages) FREESCALE

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Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

27-11

Packet-Level Interface

Transaction-Level Interface

Transmission begins when the USB host

controller fetches a TxBD containing an IN token

and loads the token to FIFO. After the IN token

is transmitted the USB host controller waits for

reception of data within expected time interval.

On reception of a correct DATA PID an RxBD is

fetched. The received data and DATA PID are

stored in receive FIFO. If RxBD[E] is set PID and

data will be moved to the buffer. While receiving

the data the USB host controller calculates

CRC16, performs bit un-stuffing. On end of

reception calculated CRC is compared to

received and octet alignment is checked,

RxBD[E] is cleared, RxBD[PID] is set according

to received DATA PID and error indications are

set if required:RxBD[CR] for failed CRC check,

RxBD[NO] for non-octet sized data and

RxBD[AB] if bit stuffing error occurred.

If no correct DATA PID or no data at all received

during the expected time interval a TO indication

in the token TxBD is set.

Transmission begins when the USB host controller

fetches a TrBD with the TOK field indicating an IN

transaction. After the IN token is generated and

transmitted, the USB host controller waits for reception

of data within the expected time interval. The received

data packet is stored in buffer reference by the TrBD.

While receiving the data the USB host controller

calculates CRC16 and performs bit un-stuffing. At end

of the packet, the calculated CRC is compared to the

received value and octet alignment is checked,

TrBD[R] is cleared, TrBD[PID] is set according to the

received DATA PID and error indications are set if

required:TrBD[CR] for failed CRC check, TrBD[NO] for

non-octet sized data and TrBD[AB] if bit stuffing error

occurred. If any of the above errors are reported,

TrBD[RXER] is also set, and a TXE1 interrupt is

generated.

If no correct DATA PID or no data at all received during

the expected time interval, a TrBD[TO] is set and a

TXE1 interrupt is generated.

If no errors occurred and TrBD[I] is set, a TXB interrupt

is generated to indicate successful completion of the

transaction.

USB In Transaction

Token

Data Transmitted by

Function

Handshake Generated

by Host

Indication on BD

Received correctly

ACK

RxBD[E]/TrBD[R] is

cleared

Received corrupted

None

RxBD[CR]/TrBD[CR} or

RxBD[AB]/TrBD[AB] or

RxBD[NO]/TrBD[NO]

None

TxBD[TO]/TrBD[TO]

SETUP

The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP

token is recognized only by a control endpoint and cannot be answered with NAK or STALL, therefore, the

host expects either an ACK or no handshake at all.

Start of

Frame

(SOF)

SOF is generated every 1 ms. The timing must be exact and is controlled by an internal timer. From the

host state machine point of view it is a packet to transmit, placed in its FIFO, transmitted as is.

Preamble

(PRE)

The PRE token signals the hub that a low-speed transaction is about to occur. The PRE token is read only

by the hub. The USB host controller generates a full-speed PRE token before sending a packet to a

low-speed peripheral.

Table 27-3. USB Tokens (continued)

Token

Description

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