MPC8280 datasheet(828/1386 Pages) FREESCALE

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Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-12

Freescale Semiconductor

27.5.2

SOF Transmission for USB Host Controller

The following section describes the mechanism used by the USB Host Controller to support the automatic

transmission of SOF tokens. This mechanism is enabled by setting USMOD[SFTE].

SOF packets should be transmitted every 1 ms. Since the time interval between two SOF packets must be

more precise than could be accomplished by software, a hardware timer is used to assert an interrupt to the

CP. When the interrupt is serviced by the CP, it prepares a SOF token and loads it to the host endpoint.

Once the SOF token is loaded to the FIFO, it is transmitted like any other packet.

Before each SOF transmission, the software should prepare a value for the frame number and CRC5 to be

transmitted in SOF token and place it in the parameter RAM (for further details please refer to

Section 27.5.5, “Frame Number (FRAME_N)”. One possible implementation would be to use the SOF

interrupt (see Section 27.5.7.5, “USB Event Register (USBER)”) to prepare the frame number for the next

SOF packet. The SFT interrupt should not be used for this purpose since it is generated before the SOF

packet is actually transmitted.

The application software should also guarantee that the USB host has completed all pending transactions

prior to the 1 ms tick so that the transmit FIFO is empty at this point. The current value of the SOF timer

may be read at any time to synchronize the software with the USB frames. See Section 27.5.7.8, “USB

Start of Frame Timer (USSFT)” for more information.

27.5.3

USB Function and Host Parameter RAM Memory Map

The USB controller parameter RAM area, shown in Table 27-4, begins at the USB base address, 0x8B00

(offset from RAM_Base). Note that the user must initialize certain parameter RAM values before the USB

controller is enabled.

Table 27-4. USB Parameter RAM Memory Map

Address

Name1

Width

Description

USB Base + 00

EP1PTR

Half word

Endpoint pointer registers 1–4. The endpoint parameter block pointers are

index pointers to each endpoint’s parameter block. Parameter blocks can

be allocated to any address divisible by 32 in the dual port RAM. See

Figure 27-6. The map of the endpoint parameter block is shown in

Table 27-5

Note: When USB host mode is set EP1PTR must be used for the host

endpoint.

USB Base + 02

EP2PTR

Half word

USB Base + 04

EP3PTR

Half word

USB Base + 06

EP4PTR

Half word

USB Base + 08

RSTATE

Word

Receive internal state. Reserved for CP use only. Should be cleared before

enabling the USB controller.

USB Base + 0C

RPTR

Word

Receive internal data pointer. Updated by the SDMA channels to show the

next address in the buffer to be accessed.

USB Base + 10

FRAME_

Half word

Frame number. See Figure 27-7

Note: The definition of this parameter is different for host mode and

function mode.

USB Base + 12

RBCNT

Half word

Receive internal byte count. A down-count value that is initialized with the

MRBLR value and decremented with every byte written by the SDMA

channels.

USB Base + 14

RTEMP

Word

Receive temp. Reserved for CP use only.

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