MPC8280 datasheet(832/1386 Pages) FREESCALE

832 / 1386 page

Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-16

Freescale Semiconductor

Table 27-6 describes FRAME_N fields.

27.5.6

USB Function Code Registers (RFCR and TFCR)

RFCR and TFCR control the value that the user would like to appear on the Address Type pins (AT1–AT3)

when the associated SDMA channel accesses memory.

Table 27-8 describes RFCR and TFCR fields.

Table 27-7. FRAME_N Field Descriptions

Bits

Name

Description

0–4

CRC5

CRC5 calculated on frame number

5–11

FRAME

NUMBER

The frame number is inserted by the application software.

01234567

Field

—

GBL

TC2

DTB

—

Figure 27-9. USB Function Code Registers (RFCR and TFCR)

Table 27-8. RFCR and TFCR Fields

Bits

Name

Description

0–1

—

Reserved, should be cleared.

GBL

Global

0 Snooping disabled

1 Snooping enabled

3–4

Byte ordering. This bit field should be set by the user to select the required byte ordering for the

data buffer. If this bit field is modified on the fly, it will take effect at the beginning of the next frame.

00 DEC (and Intel) convention is used for byte ordering—swapped operation. It is also called

little-endian byte ordering. The transmission order of bytes within a buffer word is reversed as

compared to the Freescale mode. This mode is supported only for 32-bit port size memory.

01 PowerPC little-endian byte ordering. As data is transmitted onto the serial line from the data

buffer, the least significant byte of the buffer double-word contains data to be transmitted

earlier than the most-significant byte of the same buffer double-word.

1X Freescale byte ordering—normal operation. It is also called big-endian byte ordering. As data

is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer

word contains data to be transmitted earlier than the least-significant byte of the same buffer

word.

TC2

Transfer code. Contains the transfer code value of TC[2] used during this SDMA channel memory

access.TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access

DTB

Data bus Indicator

0 Use 60x bus for SDMA operation

1 Reserved

—

Reserved, should be cleared.

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