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MPC8280 Datasheet(PDF) 829 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 829 Page - Freescale Semiconductor, Inc

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Universal Serial Bus Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
27-13
Once initialized, the parameter RAM values do not normally need to be accessed by user software. They
should only be modified when no USB activity is in progress.
27.5.4
Endpoint Parameters Block Pointer (EPxPTR)
The endpoint parameter block pointers (EPxPTR) are DPRAM indices to an endpoint’s parameter block.
The parameter block can be allocated to any address that is divisible by 32. The format of the endpoint
pointer registers (EPxPTR) is shown in Figure 27-6.
The map of the endpoint parameter block is shown in Table 27-5.
USB Base + 18
RXUSB_
Data
Word
Rx Data temp
USB Base + 1C
RXUPTR
Half word
Rx microcode return address temp
1 The items in boldface should be initialized by the user before the USB controller is enabled; other values are initialized
by the CP.
0
10
11
15
Field
Endpoint Index Pointer
—
R/W
R/W
Reset
—
Addr
USB base + 0x00 (EP1PTR), 0x02 (EP2PTR), 0x04 (EP3PTR), 0x06 (EP4PTR)
Figure 27-6. Endpoint Pointer Registers (EP
xPTR)
Table 27-5. Endpoint Parameter Block
Offset1
Name2
Width
Description
0x00
RBASE
16 bits
RxBD/TxBD base addresses. Define the starting location in dual-port RAM for the
USB controller’s TxBDs and RxBDs. This provides flexibility in how BDs are
partitioned. Setting W in the last BD in each list determines how many BDs to allocate
for the controller’s send and receive sides. These entries must be initialized before the
controller is enabled. Overlapping USB BD tables with another serial controller’s BDs
causes erratic operation. RBASE and TBASE values should be divisible by 8.
When using the transaction-level interface in host mode, TBASE points to the TrBD
ring, and RBASE is unused.
0x02
TBASE
16 bits
0x04
RFCR
8 bits
Rx/Tx function code. Controls the value to appear on AT[1–3] when the associated
SDMA channel accesses memory and the byte-ordering convention.
0x05
TFCR
8 bits
Table 27-4. USB Parameter RAM Memory Map (continued)
Address
Name1
Width
Description



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