MPC8280 datasheet(830/1386 Pages) FREESCALE

830 / 1386 page

Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-14

Freescale Semiconductor

0x06

MRBLR

16 bits

Maximum receive buffer length. Defines the maximum number of bytes the MPC8280

writes to the USB receive buffer before moving to the next buffer. MRBLR must be

divisible by 4. The MPC8280 can write fewer data bytes to the buffer than the MRBLR

value if a condition such as an error or end-of-packet occurs, but it never exceeds

MRBLR. Therefore, user-supplied buffers should never be smaller than MRBLR.

MRBLR is not designed to be changed dynamically for the currently active RxBD

during USB operation; however, MRBLR can be modified safely for the next and

subsequent RxBDs using a single bus cycle with one 16-bit move (not two 8-bit bus

cycles back-to-back).

Transmit buffers for the USB controller are not affected by the MRBLR value. Transmit

buffer lengths can vary individually, as needed. The number of bytes to be sent is

chosen by programming TxBD[Data Length].

When using the transaction-level interface in host mode, this field is used by the CP

and does not have to be initialized by the user.

0x08

RBPTR

16 bits

RxBD pointer. Points to the next BD the receiver will transfer data to when it is in an

idle state or to the current BD while processing a frame. Software should initialize

RBPTR after reset. When the end of the BD table is reached, the CP initializes this

pointer to the value programmed in RBASE. Although the user does not need to write

RBPTR in most applications (except initialization), it can be changed when the

receiver is disabled or when no receive buffer is being used.

When using the transaction-level interface in host mode, this field is unused.

0X0A

TBPTR

16 bits

TxBD pointer. Points to the next BD that the transmitter will transfer data from when it

is in an idle state or to the current BD during frame transmission. TBPTR should be

initialized by the software after reset. When the end of BD table is reached, the CP

initializes this pointer to the value programmed in the TBASEn entry. Although the

user never needs to write TBPTR, in most applications (except initialization), it can be

changed when the transmitter is disabled or when no transmit buffer is being used.

0X0C

TSTATE3

32 bits

Transmit internal state. Reserved for CP use only. Should be cleared before enabling

the USB controller.

0x10

TPTR3

32 bits

Transmit internal data pointer. Updated by the SDMA channels to show the next

address in the buffer to be accessed.

0x14

TCRC3

16 bits

Transmit temp CRC. Reserved for CP use only.

0x16

TBCNT3

16 bits

Transmit internal byte count. A down-count value that is initialized with the TxBD data

length and decremented with every byte read by the SDMA channels.

0x18

TTEMP

32 bits

Tx temp

0x1C

TXUSBU

_PTR

16 bits

Tx microcode return address temp

0x1E

HIMMR

16 bits

When using the transaction-based interface in host mode, this field must be

programmed to match the high 16 bits of the IMMR. Otherwise, this field is unused.

Offset from endpoint parameter block base.

2 Note that the items in boldface should be initialized by the user.

3 These parameters need not be accessed in normal operation but may be helpful for debugging.

Table 27-5. Endpoint Parameter Block (continued)

Offset1

Name2

Width

Description

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