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MPC8280 Datasheet(PDF) 841 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 841 Page - Freescale Semiconductor, Inc

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Universal Serial Bus Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
27-25
Data length represents the number of octets that the CP has written into this BD’s buffer. It is written once
by the CP as the BD is closed.
3
I
Interrupt
0 No interrupt is generated after this buffer has been filled.
1 The RXB bit in the USB event register will be set when this buffer has been
completely filled by the CP, indicating the need for the CPU core to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
4
L
Last. This bit is set by the USB controller when the buffer is closed due to detection
of end-of-packet condition on the bus, or as a result of error. Written by the USB
controller after the received data has been placed into the associated data buffer.
0 Buffer does not contain the last byte of the message.
1 Buffer contains the last byte of the message.
5
F
First. This bit is set by the USB controller when the buffer contains the first byte of a
packet. Written by the USB controller after the received data has been placed into the
associated data buffer.
0 Buffer does not contain the first byte of the message
1 Buffer contains the first byte of the message
6–7
—
Reserved, should be cleared
8–9
PID
Packet ID. This bit field is set by the USB controller to indicate the type of the packet.
This bit is valid only if the USB RXBD[F] is set. Written by the USB controller after the
received data has been placed into the associated data buffer.
00 Buffer contains DATA0 packet
01 Buffer contains DATA1 packet
10 Buffer contains SETUP packet. This option can never be set on host RxBD
10
—
Reserved, should be cleared
11
NO
Rx non-octet aligned packet. A packet that contained a number of bits not exactly
divisible by eight was received. Written by the USB controller after the received data
has been placed into the associated data buffer.
12
AB
Frame aborted. Bit stuff error occurred during reception. Written by the USB
controller after the received data has been placed into the associated data buffer.
13
CR
CRC error. This frame contains a CRC error. The received CRC bytes are always
written to the receive buffer. Written by the USB controller after the received data has
been placed into the associated data buffer.
14
OV
Overrun. A receiver overrun occurred during reception. Written by the USB controller
after the received data has been placed into the associated data buffer.
15
—
Reserved, should be cleared
0x02
0–15
Data length
Data length is the number of octets that the CP has written into this BD’s data buffer.
It is written once by the CP as the BD is closed.
Note: The actual amount of memory allocated for this buffer should be greater than
or equal to the contents of the MRBLR.
0x04
0–31
Rx data
buffer
pointer
The receive buffer pointer, which always points to the first location of the associated
data buffer, must be divisible by 4. The buffer may reside in either internal or external
memory
Table 27-16. USB Rx BD Fields (continued)
Offset
Bit
Name
Description



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