MPC8280 datasheet(840/1386 Pages) FREESCALE

840 / 1386 page

Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-24

Freescale Semiconductor

27.6.1

USB Receive Buffer Descriptor (Rx BD) for Host and Function

The CP reports information about each buffer of received data using Rx BDs. The CP closes the current

buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current buffer

is full. Additionally, it closes the buffer on the following conditions:

•

End of packet detected

•

Overrun error occurred

•

Bit stuff violation detected

As shown in Figure 27-18, the first word of the Rx BD contains status and control bits. These bits are

prepared by the user before reception and are set by the CP after the buffer has been closed. The second

word contains the data length—in bytes—that was received. The third and fourth words contain a pointer

that always points to the beginning of the received data buffer.

The RxBD is identical for both the host mode (when using the packet-level interface) and the function

mode. There are no RxBDs in host mode when using the transaction-level interface.

Table 27-16 describes USB receive buffer descriptor fields.

23456

789

OFFSET + 0

—

—PID

—

OFFSET + 2

DATA LENGTH

OFFSET + 4

RX DATA BUFFER POINTER

OFFSET + 6

Figure 27-18. USB Receive Buffer Descriptor (Rx BD)1,2

1 Entries in boldface must be initialized by the user.

2 All fields should be written by the CPU core before enabling the USB.

Table 27-16. USB Rx BD Fields

Offset

Bit

Name

Description

0x00

Empty

0 The data buffer associated with this Rx BD has been filled with received data, or

data reception has been aborted due to an error condition. The CPU core is free

to examine or write to any fields of this Rx BD. The CP will not use this BD again

while the E-bit remains zero.

1 The data buffer associated with this BD is empty, or reception is currently in

progress. This Rx BD and its associated receive buffer are owned by the CP. Once

the E-bit is set, the CPU core should not write any fields of this Rx BD.

—

Reserved, should be cleared

Wrap (Final BD in table)

0 This is not the last BD in the Rx BD table.

1 This is the last BD in the Rx BD table. After this buffer has been used, the CP will

receive incoming data into the first BD in the table (the BD pointed to by RBASE).

The number of Rx BDs in this table is programmable and is determined only by the

W-bit and the overall space constraints of the dual-port RAM.

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