MPC8280 datasheet(837/1386 Pages) FREESCALE

837 / 1386 page

Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

27-21

Table 27-13 describes USBER fields.

27.5.7.6

USB Mask Register (USBMR)

The USBMR is a 16-bit read/write register (0x11B74) that has the same bit formats as the USB event

zero, the corresponding interrupt in the USBER will be masked. This register is cleared at reset.

27.5.7.7

USB Status Register (USBS)

The USB status register, described in Figure 27-15 and Table 27-14, is a read-only register that allows the

user to monitor real-time status condition on the USB lines.

Table 27-13. USBER Fields

Bit

Name

Description

0–4

—

Reserved, should be cleared.

SFT

The start-of-frame timer (USSFT[SFT]) wrapped from 11,999 to 0.

RESET

Reset condition detected. USB reset condition was detected asserted.

IDLE

IDLE status changed. A change in the status of the serial line was detected. The real time

suspend status is reflected in the USB status register.

8–11

TXEx

Tx error. An error occurred during transmission for End Point x (packet not acknowledged

or underrun).

SOF

Start of frame. A start of frame packet was received. The packet is stored in the FRAME_N

parameter ram entry.

BSY

Busy condition. Received data has been discarded due to a lack of buffers. This bit is set

after the first character is received for which there is no receive buffer available.

TXB

Tx buffer. A buffer has been transmitted. This bit is set once the transmit data of the last

character in the buffer was written to the transmit FIFO (if L=0 (last bit)) or after the last

character was transmitted on the line (if L=1).

RXB

Rx buffer. A buffer has been received. This bit is set after the last character has been written

to the receive buffer and the Rx BD is closed.

Field

—

IDLE

Reset

0000_0000

R/W

Addr

0x11B77

Figure 27-15. USB Status Register (USBS)

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