MPC8280 datasheet(892/1386 Pages) FREESCALE

892 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-2

Freescale Semiconductor

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Uses 64-bit data transactions for reading and writing data in BDs

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Supports automatic routing in transparent mode using negative empty polarity

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Supports inverted data per channel

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Supports super channel synchronization in transparent mode (slot synchronization)

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Supports in-line synchronization in transparent mode (synchronization on a pattern of 1 or 2 bytes)

29.1

MCC Operation Overview

Each MCC relies upon its corresponding SI block as its physical interface to a TDM. Once an SI’s TDM

has been programmed to contain MCC-related timeslots (accomplished via SIRAM programming) and has

been enabled, the SI clocks data out of an MCC channel's TX FIFO or clocks data into an MCC channel's

RX FIFO as appropriate. Note that the SI contains no data buffering; data moving to or from an MCC

channel’s FIFO is clocked directly through the SI to or from the TDM data lines.

Activity in an MCC channel’s FIFO triggers a request to the CPM. The CPM then uses a variety of

MCC-related data structures to handle that channel’s traffic. MCC global parameters govern the overall

state of the MCC block and also contain some threshold settings and base pointers used by all channels for

their operation. There is also one set of channel-specific parameters and channel-extra parameters per

MCC channel, containing protocol state information for that channel and pointers to that particular

channel's receive and transmit buffer descriptors. These parameter RAM areas are described in more detail

in the following sections.

Note that the channel-specific parameter area may be interpreted differently depending on what protocol

is being used on that particular channel, whether it is HDLC, transparent, or SS7. If an MCC channel is

being used in conjunction with AAL1 CES, there are additional programming model changes that take

place. Also, if a TDM is programmed to make use of superchannelled MCC timeslots, a structure called

the Superchannel Table is also used. All these parameter RAM areas are described in more detail in the

following sections.

29.1.1

MCC Data Structure Organization

Each MCC uses the following data structures:

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Global MCC parameters (common to all the 128 channels of that MCC) placed in the DPRAM

from the offset (relative to the DPRAM base address) defined in Table 14-10 on page 14-22.

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Channel-specific parameters. In HDLC and transparent modes each channel uses 64 bytes of

specific parameters placed in the DPRAM at offset 64*CH_NUM (relative to the DPRAM base

address). In SS7 mode each channel uses 128 bytes of specific parameters placed DPRAM at offset

128*CH_NUM. CH_NUM is the channel number (0–127 for MCC1 and 128–255 for MCC2).

Channel-specific parameters are described in the following sections:

— Section 29.3.1, “Channel-Specific HDLC Parameters”

— Section 29.3.2, “Channel-Specific Transparent Parameters”

— Section 29.3.4, “Channel-Specific SS7 Parameters”

Note that the DPRAM memory corresponding to the inactive channels can be used for other

purposes.

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