MPC8280 datasheet(896/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-6

Freescale Semiconductor

Table 29-2. Channel-Specific Parameters for HDLC

Offset1

Name

Width

Description

0x00

TSTATE

Word

Tx internal state. To start a transmitter channel the user must write to TSTATE

0xHH80_0000. HH is the TSTATE high byte described in Section 29.3.1.1, “Internal

Transmitter State (TSTATE)—HDLC Mode.”

0x04

ZISTATE

Word

Zero-insertion machine state. User-initialized to one of the following values:

0x10000207 for regular channel transmitting all 1s before first frame of data

0x00000207 for regular channel transmitting flags before first frame of data

0x30000207 for inverted channel transmitting all 1s before first frame of data

0x20000207 for inverted channel transmitting flags before first frame of data

Note: Used in conjunction with ZIDATA0 and ZIDATA1.

0x08

ZIDATA0

Word

Zero-insertion high word data buffer. User-initialized to one of the following values:

0xFFFFFFFF allows transmission of all 1s before first frame of data

0x7E7E7E7E allows transmission of flags before first frame of data

Note: Used in conjunction with ZISTATE and ZIDATA1.

0x0C

ZIDATA1

Word

Zero-insertion low word data buffer. User-initialized to one of the following values:

0xFFFFFFFF allows transmission of all 1s before first frame of data

0x7E7E7E7E allows transmission of flags before first frame of data

Note: Used in conjunction with ZISTATE and ZIDATA0.

0x10

TBDFlags Hword TxDB flags, used by the CP (read-only for the user)

0x12

TBDCNT

Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only

for the user)

0x14

TBDPTR

Word

Tx internal data pointer. Points to current absolute data address of channel, used by the

CP (read-only for the user)

0x18

INTMSK

Hword Channel’s interrupt mask flag. See Section 29.3.3.1.1, “Interrupt Circular Table Entry

and Interrupt Mask (INTMSK) —AAL1 CES.”

0x1A

CHAMR

Hword Channel mode register. See Section 29.3.1.3, “Channel Mode Register

(CHAMR)—HDLC Mode.”

0x1C

TCRC

Word

Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only

for the user)

0x20

RSTATE

Word

Rx internal state. To start a receiver channel the user must write to RSTATE

0xHH80_0000. HH is the RSTATE high byte described in Section 29.3.1.4, “Internal

Receiver State (RSTATE)—HDLC Mode.”

0x24

ZDSTATE

Word

Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and

0x20FFFFE0 for inverted channel)

0x28

ZDDATA0

Word

Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)

0x2C

ZDDATA1

Word

Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)

0x30

RBDFlags Hword RxBD flags, used by the CP (read-only for the user)

0x32

RBDCNT

Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only

for the user)

0x34

RBDPTR

Word

Rx internal data pointer. Points to current absolute data address of channel, used by

the CP (read-only for the user)

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