MPC8280 datasheet(899/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-9

Table 29-4. CHAMR Field Descriptions

Bits

Name

Description

MODE This mode bit determines whether the HDLC or transparent mode is used. It also determines how other

CHAMR bits are interpreted.

0 Transparent mode. See Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.”

1 HDLC mode

POL

Enable polling. POL enables the transmitter to poll the TxBDs.

0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).

1 Polling is enabled.

POL is used to optimize the use of the external bus. Software should always set POL at the beginning of

a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready in the

transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the end of a

multi-frame transmission). To minimize useless transactions on the external bus, software should always

prepare the new BD, or multiple BDs, and set BD[R] before enabling polling.

Must be set.

IDLM

Idle mode.

0 No idle patterns are sent between frames. After sending NOF+1 flags, the transmitter starts sending

the data of the frame. If the transmission is between frames and the frame buffers are not ready, the

transmitter sends flags until it can start transmitting the data.

1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller than the

PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in HDLC. Mode flags precede the

actual data. When IDLM = 1, at least one idle pattern is sent between adjacent frames. If the

transmission is between frames and the frame buffer is not ready, the transmitter sends idle characters.

When data is ready, the NOF+1 flags are sent followed by the data frame.

If IDLE mode is selected and NOF = 1, the following sequence is sent:

......init value, FF, FF, flag, flag, data, ........

The init value before the idle will be ones.

—

This bit must be cleared.

0 Normal bit order (transmit/receive the lsb of each octet first)

Reversed bit order (transmit/receive the msb of each octet first)

6–7

—

These bits must be cleared.

CRC

Selects the type of CRC when HDLC channel mode is used.

0 16-bit CCITT-CRC

1 32-bit CCITT-CRC

—

This bit must be cleared.

Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer

that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4 (n is any

integer larger than 0).

11–12

RQN

Receive queue number. Specifies the receive interrupt queue number.

00 Queue number 0.

01 Queue number 1.

10 Queue number 2.

11 Queue number 3.

13–15

NOF

Number of flags. NOF defines the minimum number of flags before frames:

000 At least 1 flag

001 At least 2 flags

....

111 At least 8 flags

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