MPC8280 datasheet(903/1386 Pages) FREESCALE

903 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-13

CHAMR fields are described in Table 29-4.

Table 29-7. CHAMR Field Descriptions—Transparent Mode

Bits

Name

Description

MODE

Channel mode. Selects either HDLC or transparent mode.

0 Transparent mode.

1 HDLC mode

POL

Enable polling. POL enables the transmitter to poll the TxBDs.

0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).

1 Polling is enabled.

POL is used to optimize the use of the external bus. Software should always set POL at the

beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers

are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame

or at the end of a multi-frame transmission). To prevent a significant number of useless transactions

on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R]

before enabling polling.

2–3

0b11

Must be set.

Empty polarity and enable polling.

0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only

if POL is set.

1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs

disregarding the value of POL.

0 Normal bit order (transmit/receive the lsb of each octet first)

1 Reversed bit order (transmit/receive the msb of each octet first)

6–7

SYNC

Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.

SYNC

Receive Transmit

Description

None

Transmitter and receiver operate with no synchronization algorithm.

RCVSYNC should be cleared or erroneous behavior may occur. If

data synchronization is not used, the beginning of receive data may

contain an arbitrary amount of bytes before actual data appears in

the receive buffer. These unrelated bytes can be data or idles that

were in the receive FIFO when reception began or can be data that

was on the line previous to the arrival of the intended data.

Slot

The first data is sent/received in the slot defined in the slot

assignment table (for super channels only). RCVSYNC should be

cleared or received data may be shifted.

8-bit

None

Receive data synchronization uses an 8-bit pattern specified by the

8 msb of RCVSYNC. The sync bytes are not written to the receive

buffer.

16-bit

None

Receive data synchronization uses a 16-bit pattern specified by

RCVSYNC. The first byte of the sync pattern will not be written to the

receive buffer. The second byte of the sync pattern will be written to

the receive buffer (first and second represent the order in which the

two bytes of the sync pattern are received on the serial channel).

8–9

—

Reserved, must be cleared.

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