MPC8280 datasheet(904/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-14

Freescale Semiconductor

29.3.2.4

Internal Receiver State (RSTATE)—Transparent Mode

In transparent mode, RSTATE functions the same as in HDLC mode. For a description, refer to Section

29.3.1.4.

29.3.3

MCC Parameters for AAL1 CES Usage

When using AAL1 CES, the structured and unstructured data are transferred between the ATM and MCC

automatically without CPU intervention. Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.”

The following subsections describe the additional parameters required for AAL1 CES.

29.3.3.1

Channel-Specific Parameters—AAL1 CES

The following are changes that occur in the channel-specific parameter RAM when using AAL1 CES.

Table 29-8 describes the additional global MCC parameters specific to CES operation.

Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data

buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4

(N is any number larger than 0).

11–12

RQN

Receive queue number. Specifies the receive interrupt queue number.

00 Queue number 0.

01 Queue number 1.

10 Queue number 2.

11 Queue number 3.

13–15

—

Reserved, must be cleared.

Table 29-8. CES-Specific Global MCC Parameters

Offset1

The offset to the CES-specific global MCC parameter RAM for MCC1 is 0x8780. For MCC2, it is 0x8880.

Name

Width

Description

0x00

CATB

Hword

CES adaptive threshold tables base address. Points to the dual-port RAM area

containing the CES slip control thresholds and the adaptive counter See Section 32.5,

“ATM-to-TDM Adaptive Slip Control.

” Should be 8-byte aligned (8 octets for each

AAL1-MCC channel). User-defined and should match the CATB value programmed in

the AAL-1 parameter RAM; see Section 32.8.1, “AAL1 CES Parameter RAM.”

0x02

—

Hword

Reserved, should be cleared during initialization.

0x04,

0x08,

0x0C,

0x10

UTAa,

UTAb,

UTAc,

UTAd,

Hword

Underrun template address for TDM

x. Points to the dual-port RAM area containing the

user-defined template to be sent during an MCC transmitter pre-underrun condition.

0x06,

0x0A,

0x0E,

0x12

UTSa,

UTSb,

UTSc,

UTSd,

Hword

Underrun template size for TDM

x. This is the size in bytes of the underrun template

buffer.

Table 29-7. CHAMR Field Descriptions—Transparent Mode (continued)

Bits

Name

Description

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