MPC8280 datasheet(906/1386 Pages) FREESCALE

906 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-16

Freescale Semiconductor

2–3

0b11

Must be set.

Empty polarity and enable polling.

0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only if

POL is set.

1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs

disregarding the value of POL.

0 Normal bit order (transmit/receive the lsb of each octet first)

Reversed bit order to be reversed (transmit/receive the msb of each octet first).

6–7

SYNC

Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.

SYNC

Receive

Transmit

Description

None

Transmitter and receiver operate with no synchronization algorithm

Slot

The first data is sent/received in the slot defined in the slot assignment

table (for super channels only)

8-bit

None

Receive data synchronization uses an 8-bit pattern specified by the 8

msb of RCVSYNC. The sync bytes will not be written to the receive

buffer

16-bit

None

Receive data synchronization uses a 16-bit pattern specified by

RCVSYNC. The first byte of the sync pattern will not be written to the

receive buffer. The second byte of the sync pattern will be written to

the receive buffer (first and second represent the order in which the

two bytes of the sync pattern are received on the serial channel).

8–9

—

Reserved, should be cleared during initialization.

Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer

that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is

any number larger than 0).

11–12 RQN

Receive queue number. Specifies the receive interrupt queue number.

00 Queue number 0

01 Queue number 1

10 Queue number 2

11 Queue number 3

CESM

Circuit emulation service mode.

Normal mode

CES mode

UDC

User-defined cell support.

0 User-defined ATM cells are not supported.

1 User-defined ATM cells are supported.

UTM

Underrun template mode.

0 Retransmit the last buffer.

1 Send the user-defined template.

Table 29-9. CHAMR Field Descriptions—CES Mode (continued)

Bits

Name

Description

MPC8280 Datasheet(PDF) 906 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 906 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL