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MPC8280 Datasheet(PDF) 909 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 909 Page - Freescale Semiconductor, Inc

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Multi-Channel Controllers (MCCs)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
29-19
0x20
RSTATE
Word
Rx internal state. To start a receiver channel the user must write to RSTATE
0xHH80_0000. HH is the RSTATE High Byte. Refer to Section 29.3.1.4, “Internal
Receiver State (RSTATE)—HDLC Mode.”
0x24
ZDSTATE
Word
Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel, and
0x20FFFFE0 for reversed bit order channel)
0x28
ZDDATA0
Word
Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
0x2C
ZDDATA1
Word
Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
0x30
RBDFlags
Hword
RxBD flags, used by the CP (read-only for the user)
0x32
RBDCNT
Hword
Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x34
RBDPTR
Word
Rx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
0x38
MFLR
Hword
Maximum frame length register. Defines the longest expected frame for this channel.
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded
and the LG flag is set in the last frame’s BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frame’s length is considered to be
everything between flags, including CRC. No more data is written into the current buffer
when the MFLR violation is detected.
0x3A
MAX_cnt
Hword
Max_length counter, used by the CP (read-only for the user)
0x3C
RCRC
Word
Temporary receive CRC, used by the CP (read-only for the user)
0x40
N
Hword
Applies to ITU-T/ANSI SS7 only. Interrupt threshold in octet counting mode (N=16). See
Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode
N_cnt
Hword
Applies to ITU-T/ANSI SS7 only. Temporary down counter for N (user initialized to the
value of N).
JTSTTmp
Word
Applies to Japanese SS7 only. Temporary storage for Time-Stamp Register Value. Used
by the CP to implement a 24-ms delay before sending FISU.
0x44
D
Hword
Signal unit to signal unit error ratio (SUERM parameter, user initialized to 256). See
Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode
0x46
D_cnt
Hword
Applies to ITU-T/ANSI SS7 only. Temporary down-counter for D (user initialized to the
value of D). D_cnt is decremented only when receive buffers are available.
JTTDelay
Applies to Japanese SS7 only. FISU retransmission delay (specified in units of 512¨µs).
According to the Japanese SS7 standard, the delay should be 24 ms and thus JTTDelay
should be programmed to 24 ms/512 µs = 46.875 (approximately 47). Hence, the user
should program JTTDelay to 0x2F and the RTSCR to generate a 1 µs time stamp period.
Refer to Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR)”.
0x48
Mask1
Word
Mask for SU filtering, bytes 0-3. See 29.3.4.4, “SU Filtering—SS7 Mode
0x4C
Mask2
Hword
Mask for SU filtering, byte 4. See 29.3.4.4, “SU Filtering—SS7 Mode
0x4E
SS7_OPT
Hword
SS7 configuration register. See Section 29.3.4.3, “SS7 Configuration Register—SS7
Mode.”
0x50
LRB1_Tmp
Word
Temporary storage, used by CP for SU filtering.
Table 29-10. Channel-Specific Parameters for SS7 (continued)
Offset1
Name2
Width
Description



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