MPC8280 datasheet(913/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-23

29.3.4.2.1

SUERM in Japanese SS7

The Japanese SS7 uses a time interval to monitor errors. If an error is present, it checks every 24 ms.

•

An error flag is set that indicates whether current frame is errored or not.

•

For every JTRDelay an error flag is checked.

•

If there is no error, decrement the counter SUERM by 1 (not below zero).

•

If there is an error, increment the counter SUERM by D.

•

If SUERM reaches T, the counter SUERM is cleared and a “signal unit error rate monitor” interrupt

is generated.

29.3.4.3

SS7 Configuration Register—SS7 Mode

The SS7 configuration register, shown on Figure 29-10 contains additional SS7 parameters.

Table 29-13 describes SS7 configuration register fields.

Table 29-12. Parameter Values for SUERM in Japanese SS7

Parameter

Definition

Value

Threshold

285

Upcount

JTRDelay

Length of interval (24ms)

0x2F

Field

—

AERM SUERM_DIS STD SF_DIS SU_FIL SEN_FIS O_ORN O_ITUT

FISU_PAD

Reset

R/W

Figure 29-10. SS7 Configuration Register (SS7_OPT)

Table 29-13. SS7 Configuration Register Fields Description

Bits

Name

Description

0–3

—

Reserved, should be cleared during initialization.

AERM

Alignment error rate monitor enable. See Section 29.3.4.3.1, “AERM Implementation.”

0 Do not enable AERM.

1 Enable AERM.

SUERM_DIS

Disable the SU error rate monitor. See Section 29.3.4.3.3, “Disabling SUERM.”

0 Enable SUERM.

1 Disables both SUERM and AERM.

STD

Standard compliance

0 ITU-T/ANSI compliant

1 Japanese SS7 compliant

SF_DIS

Discard short frames (less than 5 octets)

0 Do not discard short frames.

1 Discard short frames.

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