MPC8280 datasheet(911/1386 Pages) FREESCALE

911 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-21

The interrupt mask provides bits for enabling/disabling each event defined in the interrupt circular table

entry. Other bits provide various channel configuration options.

ECHAMR fields are described in Table 29-11.

Field MODE0

—

OCT

SUERM

FISU

—

TXB

—

AERM NID IDL MRF RXF BSY RXB

Reset

No reset value

R/W

Offset

0x18

Field MODE1 POL

IDLM

—

RQN

NOF

Reset

No reset value

R/W

Offset

0x1A

Figure 29-9. Extended Channel Mode Register (ECHAMR)

Table 29-11. ECHAMR Fields Description

Bits

Name

Description

0,16

MODE0

MODE1

00 Transparent mode

01 HDLC mode

10 Reserved

11 SS7 mode (This is the required bit setting for an MCC to perform SS7.)

1, 5, 8

Reserved, should be cleared during initialization.

2–4

6–7

9–15

INTMSK

Interrupt mask bits. These bits are used for enabling/disabling the reporting of each possible event

defined in the interrupt circular table entry. See Section 29.8.1.1, “Interrupt Circular Table Entry.”

0 Disabled

1 Enable

POL

Enable polling. POL enables the transmitter to poll the TxBDs.

0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).

1 Polling is enabled.

POL is used to optimize the use of the external bus. Software should always set POL at the

beginning of a transmit sequence of one or more frames. The CP clears POL when no more

buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the

end of a frame or at the end of a multi-frame transmission). To prevent a significant number of

useless transactions on the external bus, software should always prepare the new BD, or

multiple BDs, and set BD[R] before enabling polling.

Reserved, must be set.

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