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MPC8280 Datasheet(PDF) 912 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 912 Page - Freescale Semiconductor, Inc |
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912 / 1386 page ![]() Multi-Channel Controllers (MCCs) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-22 Freescale Semiconductor 29.3.4.2 Signal Unit Error Monitor (SUERM)—SS7 Mode The microcode maintains the signal unit error rate monitor as described in ITU-T Q.703 paragraph 10, and ANSI T1.111-1996 paragraph 10. The microcode uses SUERM, N, N_cnt, D, D_cnt and T parameters for the leaky-bucket implementation of the SU error monitor. • After every N octets received while in octet counting mode, SUERM is incremented and an interrupt request can be generated (SUERM) depending on the interrupt mask. • After D error-free frames have been received, SUERM is decremented. SUERM will not be decremented below zero. • If SUERM reaches T, the SUERM is cleared and an interrupt is generated. 19 IDLM Idle mode. 0 No idle patterns are transmitted between frames. After transmitting NOF+1 flags, the transmitter starts sending the data of the frame. If the transmission is between frames and the frame buffers are not ready, the transmitter sends flags until it can start transmitting the data received for SS7 operation. 1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller than the PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in SS7. Mode flags precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent frames. If the transmission is between frames and the frame buffer is not ready, the transmitter sends idle characters. When data is ready, the NOF+1 flags are sent followed by the data frame. If IDLE mode is selected and NOF = 1, the following sequence is sent: ......init value, FF, FF, flag, flag, data, ........ The init value before the idle will be ones. 20–25 — Reserved, should be cleared during initialization. 10 TS Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4 (n is any integer larger than 0). 11–12 RQN Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. 13–15 NOF Number of flags. NOF defines the minimum number of flags before frames: 000 - at least 1 flag 001 - at least 2 flags .... 111 - at least 8 flags Note that items in bold must be initialized by the user. Table 29-11. ECHAMR Fields Description (continued) Bits Name Description |
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