MPC8280 datasheet(910/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-20

Freescale Semiconductor

29.3.4.1

Extended Channel Mode Register (ECHAMR)—SS7 Mode

The extended channel mode register (ECHAMR) is a user-initialized register, shown in Figure 29-9 It

includes both the interrupt mask bits and channel configuration bits.

0x54

LRB2_Tmp

Hword

Temporary storage, used by CP for SU filtering.

0x56

SUERM

Hword

Signal unit error rate monitor counter (user initialized to 0). See Section 29.3.4.2, “Signal

Unit Error Monitor (SUERM)—SS7 Mode.”

0x58

LRB1

Word

Four first bytes of last received signal unit. Used by CP for SU filtering. See 29.3.4.4,

“SU Filtering—SS7 Mode.”

0x5C

LRB2

Hword

Fifth byte of last received signal unit. Used by CP for SU filtering. See 29.3.4.4, “SU

Filtering—SS7 Mode

0x5E

Hword

SUERM threshold value (user initialized to 64). See Section 29.3.4.2, “Signal Unit Error

Monitor (SUERM)—SS7 Mode.”

0x60

LHDR

Word

The BSN, BIB, FSN, FIB fields of last transmitted signal unit and result of CRC. Used by

CP for automatic FISU transmission.

0x64

LHDR_Tmp

Word

Temporary storage, used by CP for automatic FISU transmission.

0x68

EFSUC

Word

Error-free signal unit counter, user initialized to 0. The counter is incremented whenever

an error-free (no CRC error, no non-octet aligned error, no short or long frame errors)

signal unit is received.

0x6C

SUEC

Word

Signal unit error counter, user initialized to 0. Incremented each time an SU is received

that contains an error. These errors are: short frame, long frame, CRC error, and

non-octet aligned error.

0x70

SS7STATE

Word

Internal state of SS7 controller, user initialized to 0.

0x74

JTSRTmp

Word

Temporary storage for time-stamp register value. Applies to Japanese SS7 only;

otherwise should be cleared. Used by the CP to implement the 24-ms delay for signal

unit error rate monitoring in Japanese SS7.

0x78

JTRDelay

Hword

FISU transmit delay (specified in units of 512us). Applies to Japanese SS7 only;

otherwise should be cleared. According to the Japanese SS7 standard, the delay should

be 24 ms and thus JTRDelay should be programmed to 24 ms/512 µs = 46.875

(approximately 47). Hence, the user should program JTRDelay to 0x2F and the RTSCR

to generate a 1 µs time stamp period. Refer to Section 14.3.8, “RISC Time-Stamp

Control Register (RTSCR)”.

0x7A

Hword

ITU threshold for AERM. If M_cnt reaches M, an AERM interrupt is generated. Note that

M is normally programmed to 5.

0x7C

M_cnt

Hword

Up-counter for M. Should be cleared during initialization.

1 The offset is relative to the dual-port RAM address + 64*CH_NUM. SS7 channel specific parameters require twice the

amount of dual-port RAM required for HDLC or Transparent channel specific parameters. Therefore for SS7 even

channel numbers (0, 2, 4, etc.) must be used and odd channel number must be left unused.

2 Items in boldface must be initialized by the user. Unless otherwise stated, all other items are managed by microcode

and should be initialized to zero.

Table 29-10. Channel-Specific Parameters for SS7 (continued)

Offset1

Name2

Width

Description

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