MPC8280 datasheet(914/1386 Pages) FREESCALE

914 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-24

Freescale Semiconductor

29.3.4.3.1

AERM Implementation

The SS7 microcode implements the ITU Q.703 alignment error rate monitor (AERM). The microcode uses

the T, SUERM, M and M_cnt parameters. The M_cnt parameter is incremented for every T errored frames.

If M_cnt reaches M, an AERM interrupt is generated to layer 3.

Note that in AERM mode no SUERM interrupt is generated. Also, the algorithm associated with D and

D_cnt is disabled as per the ITU specification.

29.3.4.3.2

AERM in Japanese SS7

To meet the Japanese AERM requirements the user must change the parameters T and D. Note that the

interrupt generated is not AERM but SUERM.

During proving, do the following:

1. Set SS7_OPT register to 0b0000 001X XX00 XXXX. The value of X doesn’t matter because these

bits do not affect the operation of the error counter.

2. Clear JTRdelay parameter to'0.'

3. Set parameters T (threshold) and D (up counter) to'1.'

4. Clear parameter SUERM (error counter) to'0.'

5. Set JTTDelay to value required to generate 24ms delay.

These settings allow FISU or LSSU transmission to be delayed by the required 24ms (JTTDelay). They

also allow the correct operation of the JT Q703 error counter and ensure that an SUERM interrupt is

generated on the first SU received in error.

SU_FIL

SU Filtering

0 Disable SU filtering.

1 Enable SU filtering.

SEN_FIS

Send FISU if first BD of frame is not ready.

0 Flags are sent if the current BD, which is the first BD of the frame, does not have its ready bit set.

1 FISUs are automatically sent if the current BD, which is the first BD of the frame, does not have

its ready bit set.

O_ORN

Enter octet counting mode (OCM) on overrun. Should be cleared if using the Japanese standard.

0 Disable entering OCM if there are no receive BDs available.

1 Enter OCM if there are no receive BDs available.

Note that when STD = 1, O_ORN = 1, and no receive buffers are ready, a ny received signal unit

is treated as an erred signal unit.

O_ITUT

Enter octet counting mode (OCM) on ITU-T conditions (after an abort sequence or when an SU is

too long). Should be cleared if using the Japanese standard.

0 Disable entering OCM on ITU-T conditions.

1 Enable entering OCM on ITU-T conditions.

12–15

FISU_PAD

Padding of the automatically transmitted FISUs. If the SEN_FISU bit is set, the CP will use the

value of FISU_PAD as a number of pad character. Please refer to PAD parameter in Section 29.9.2,

“Transmit Buffer Descriptor (TxBD).”

Table 29-13. SS7 Configuration Register Fields Description (continued)

Bits

Name

Description

MPC8280 Datasheet(PDF) 914 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 914 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL