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MPC8280 Datasheet(PDF) 908 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 908 Page - Freescale Semiconductor, Inc

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Multi-Channel Controllers (MCCs)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
29-18
Freescale Semiconductor
•
Automatic retransmission of signal units (for link-status signal unit (LSSU) retransmission)
•
Automatic discard of identical FISUs and LSSUs using a user-defined mask
•
Octet counting mode in case of long signal units and receiver overrun
•
Five circular interrupt tables with programmable size and overflow identification—one for
transmit and four for receive.
•
Global or individual channel loop modes
•
Efficient bus usage (no bus usage for inactive channels or for active channels with nothing to send)
•
Efficient control of interrupts to the CPU
•
Supports external BD tables
•
Uses on-chip dual-port RAM for parameter storage
•
Uses 64-bit data transactions for reading and writing data in BDs
Table 29-10 describes channel-specific parameters for SS7. Note that a given parameter location may have
a different definition depending on the standard used (ITU-T/ANSI or Japanese standard).
Table 29-10. Channel-Specific Parameters for SS7
Offset1
Name2
Width
Description
0x00
TSTATE
Word
Tx internal state. The user must write to TSTATE 0xHH80_0000. HH is the TSTATE High
Byte. Refer to Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.”
0x04
ZISTATE
Word
Zero-insertion machine state. User-initialized to one of the following values:
0x10000207 for regular channel transmitting all 1s before first frame of data
0x00000207 for regular channel transmitting flags before first frame of data
0x30000207 for inverted channel transmitting all 1s before first frame of data
0x20000207 for inverted channel transmitting flags before first frame of data
Note: Used in conjunction with ZIDATA0 and ZIDATA1.
0x08
ZIDATA0
Word
Zero-insertion high word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA1.
0x0C
ZIDATA1
Word
Zero-insertion low word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA0.
0x10
TBDFlags
Hword
TxBD flags, used by the CP (read-only for the user)
0x12
TBDCNT
Hword
Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x14
TBDPTR
Word
Tx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
0x18
ECHAMR
Word
Extended channel mode register. See 29.3.4.1, “Extended Channel Mode Register
(ECHAMR)—SS7 Mode.”
0x1C
TCRC
Word
Temporary transmit CRC. Temporary value of CRC calculation result, used by the CP
(read-only for the user)



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